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- In relation to this article, we declare that there is no conflict of interest.
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Received February 12, 2026
Accepted May 3, 2026
Available online August 25, 2026
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This is an Open-Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/bync/3.0) which permits
unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
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Characteristics of the MoS2 Memory Thin Film Transistor With Au Nanoparticles Embedded as Charging Elements
https://doi.org/10.1007/s11814-026-00743-x
Abstract
MoS2-based nonvolatile memory devices, including a capacitor and thin-film transistors (TFTs), were fabricated in a
metal-MoS2-insulator-Si (MMIS) architecture with interfacial Au nanoparticles (Au NPs) serving as charge-storage nodes
between monolayer MoS2 and the gate dielectric. An n-type SiO2 layer (10 nm) was functionalized with an APTES selfassembled
monolayer to enable dense Au NP assembly, yielding an M-capacitor with pronounced hysteresis in capacitance-voltage
(C-V) characteristics. MoS2 TFTs were further realized on 300 nm n-type SiO2, either without Au NPs
(M-TFT) or with the Au NP interlayer (MM-TFT). Solution-processed MoS2 prepared by chemical exfoliation was characterized
by TEM, AFM, Raman spectroscopy, and XPS. The M-capacitor exhibited a flat-band voltage shift (ΔVFB) of
1.73 V under a±5 V sweep, while the MM-TFT showed a threshold-voltage shift (ΔVTH) of 6.32 V for a+10 to -30 V
gate sweep, confirming efficient interfacial charge trapping.
